In switching circuits such as synchronous buck converters, half bridge converter and inverters, two power MOSFETs are switched in complementary fashion. As modeled in FIG. 1, a switching circuit generally designated 110, includes two MOSFETs 100 and 150 connected in series and across a voltage source 105. MOSFETs 100 and 150 are typically referred to as high side and low side MOSFETs respectively.
To initiate a switching cycle, the low side MOSFET 150 is first turned off. This forces the body diode of MOSFET 150 to turn on and drive the current. After a delay, the high side MOSFET 100 is turned on, forcing the body diode to turn off. However, the turn off process of the body diode results in an abrupt termination of its recovery current. This recovery current flows in the parasitic inductances LDHS, LSHS, LDLS, and LSLS as well as in trace inductances LTRCS, LTRCH and LTRCL of the switching circuit 110.
The abrupt termination of the current in these inductances leads to severe oscillations in the switching circuit 110, commonly known as ringing. The inductances in the switching path also slow down the switching speed and cause additional losses. As switching frequencies continue to increase, these losses become more significant, restricting the performance of the switching circuit 110.
A variety of prior art solutions exist to minimize the lead inductances. For example, some prior art solutions co-package the high side and low side MOSFETs and place the two dies side by side and connect them internally to the package with wire. Such co-packaging avoids some of the inductances in the traces outside but does not fully eliminate them.
It is known in the prior art to stack MOSFET dies one over the other with a metallic tab sandwiched between them. Examples include U.S. Pat. No. 6,777,786 to Estacio which discloses a semiconductor device including stacked dies mounted on a leadframe, U.S. Pat. No. 7,029,947 to Joshi which discloses a flip chip in leaded molded package with two dies, and US Patent Application Publication No. 2001/0052641 to Kuo et al. which discloses a power semiconductor device including upper and lower dies. While these references disclose staking MOSFET die, such stacking is restricted to a single MOSFET in a package with the aim of reducing the number of bond wires and manufacturing costs. Even though these solutions include the stacking of two dies, the top die is flipped so that the die can be ultimately connected together as a single MOSFET device. No attempt has been made in the prior art to stack dual MOSFETs operating in a complementary fashion.
There is therefore a need in the art for a stacked dual MOSFET package which overcomes the limitations of the prior art. There is also a need for a stacked dual MOSFET package for implementing circuits such as synchronous buck converters, half bridge converters and inverters having MOSFETs switched in complementary fashion. There is a further need for a stacked dual MOSFET package that minimizes the lead and interconnection inductances to a level not possible in the existing art. There is also a need for a stacked dual MOSFET package that provides higher efficiencies and reduced ringing during switching operation.